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Disambiguation of "Olivo, Piero"

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Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block.

, , , and . DFT, page 271-278. IEEE Computer Society, (1993)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Piero Kirchner

Multiplex-System für digitale Datenströme in multimedialen Anwendungen. TU Ilmenau, (2009)

Cristian Olivo

Michael Olivo

Piero Zappi

Piero Domizi

 

Other publications of authors with the same name

Analysis and Design of Linear Finite State Machines for Signature Analysis Testing., , and . IEEE Trans. Computers, 40 (9): 1034-1045 (1991)Design space exploration of latency and bandwidth in RRAM-based solid state drives., , , , and . NVMTS, page 1-4. IEEE, (2015)Improving performance and reliability of NOR-Flash arrays by using pulsed operation., , and . Microelectron. Reliab., 46 (9-11): 1478-1481 (2006)Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers., , , , , , and . ACM Trans. Embed. Comput. Syst., 14 (1): 7:1-7:24 (2015)An Automated Test Equipment for Characterization of Emerging MRAM and RRAM Arrays., , , , , , , and . IEEE Trans. Emerg. Top. Comput., 6 (2): 269-277 (2018)Dynamic effects in the detection of bridging faults in CMOS ICs., , and . J. Electron. Test., 3 (3): 197-205 (1992)A novel critical path heuristic for fast fault grading., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (4): 544-548 (1991)Overerase phenomena: an insight into flash memory reliability., , and . Proc. IEEE, 91 (4): 617-626 (2003)Architectural and Integration Options for 3D NAND Flash Memories., , , and . Computers, 6 (3): 27 (2017)RRAM Reliability/Performance Characterization through Array Architectures Investigations., , , , and . ISVLSI, page 327-332. IEEE Computer Society, (2015)