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Novel Test Pattern Generators for Pseudoexhaustive Testing.

, , and . IEEE Trans. Computers, 49 (11): 1228-1240 (2000)

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SIESTA: a multi-facet scan design system., , , and . EURO-DAC, page 246-251. IEEE Computer Society Press, (1992)An O(n) algorithm for width determination of power/ground routes for VLSI circuits., and . Integr., 4 (4): 345-355 (1986)Built-in test for folded programmable logic arrays., and . Microprocess. Microsystems, 11 (6): 319-329 (1987)BALLAST: a methodology for partial scan design., , and . FTCS, page 118-125. IEEE Computer Society, (1989)Scan Path with Look Ahead Shifting (SPLASH)., and . ITC, page 696-704. IEEE Computer Society, (1986)A class of min-cut placement algorithms.. DAC, page 284-290. ACM, (1977)Some theoretical aspects of algorithmic routing., and . DAC, page 23-31. ACM, (1977)A Note on Three-Valued Logic Simulation.. IEEE Trans. Computers, 21 (4): 399-402 (1972)Functional Partitioning and Simulation of Digital Circuits.. IEEE Trans. Computers, 19 (11): 1038-1046 (1970)Test Schedules for VLSI Circuits Having Built-In Test Hardware., and . IEEE Trans. Computers, 35 (4): 361-367 (1986)