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An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme.

M. Tsai, P. Kuo, J. Lin, and M. Sheu. ISCAS, page 1-4. IEEE, (2018)

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Pey-Jin Lin

Lin Lin

Other publications of authors with the same name

Projection Matching Pursuit based DoA Estimation Scheme and its FPGA Implementation.W. Ma, K. Chang, K. Chen, Y. Hwang, and J. Lin. ISOCC, page 109-110. IEEE, (2019)MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging.S. Wang, Y. Tien, Y. Hwang, J. Lin, and G. Wu. APCCAS, page 143-145. IEEE, (2016)A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications.M. Sheu, C. Tsai, M. Tsai, S. Hsia, S. Morsalin, and J. Lin. Sensors, 21 (19): 6591 (2021)Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design.J. Lin, Z. Hong, J. Wu, X. Tung, C. Yang, and Y. Yen. Sensors, 22 (15): 5696 (2022)Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme.Y. Hwang, J. Lin, and M. Sheu. IEEE Trans. Very Large Scale Integr. Syst., 20 (2): 361-366 (2012)Low Power Pulse Generator Design Using Hybrid Logic.J. Lin, Y. Hwang, and M. Sheu. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (6): 1266-1268 (2010)Low Power Multipliers Using Enhenced Row Bypassing Schemes.Y. Hwang, J. Lin, M. Sheu, and C. Sheu. SiPS, page 136-141. IEEE, (2007)Semantic Lung Segmentation Using Convolutional Neural Networks.C. Chang, J. Lin, M. Lee, and C. Palm. Bildverarbeitung für die Medizin, page 75-80. Springer, (2020)A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic.J. Lin, Y. Hwang, and M. Sheu. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2755-2757 (2010)Low Power Multiplier Designs Based on Improved Column Bypassing Schemes.Y. Hwang, J. Lin, M. Sheu, and C. Sheu. APCCAS, page 594-597. IEEE, (2006)

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Disambiguation of "Lin, Jin-Fa"

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An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme.

Please choose a person to relate this publication to

Pey-Jin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lin, Jin-Fa"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme.

Please choose a person to relate this publication to

Pey-Jin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme.