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Disambiguation of "de la Torre, Eduardo"

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Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification.

, , , and . DCIS, page 1-7. IEEE, (2019)

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Martino La Torre

Hector la Torre

Luis La Torre

Silvia Eunice Gutiérrez de la Torre Julius-Maximilians-Universität Würzburg

Eduardo La Riega

 

Other publications of authors with the same name

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs., , , and . IEEE Trans. Computers, 71 (11): 2903-2914 (2022)A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC., , , , , and . CPS Summer School, PhD Workshop, volume 2457 of CEUR Workshop Proceedings, page 107-118. CEUR-WS.org, (2019)Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion., , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 1057-1061. Springer, (2004)Execution modeling in self-aware FPGA-based architectures for efficient resource management., , , , , and . ReCoSoC, page 1-8. IEEE, (2015)Message from the chairs., , , and . ReCoSoC, page 1. IEEE, (2015)A dynamic communication strategy for the distributed ATPG system DPLATON., , , and . EURO-DAC, page 271-276. IEEE Computer Society, (1993)Introduction to the Special Section on FPGAs Technology and Applications., , and . Comput. Electr. Eng., (2016)Accelerating the evolution of a systolic array-based evolvable hardware system., and . Microprocess. Microsystems, (2018)Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation., , , , , , and . IEEE Access, (2020)Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing., , , , , and . IEEE Trans. Computers, 62 (8): 1481-1493 (2013)