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Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells., , , и . ISCAS, стр. 1122-1125. IEEE, (2014)Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells., , и . ISLPED, стр. 242-247. ACM, (2016)Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells., , , и . ESSDERC, стр. 77-80. IEEE, (2012)Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM., , , , и . APCCAS, стр. 471-474. IEEE, (2012)Design and analysis of ultra-thin-body SOI based subthreshold SRAM., , , , и . ISLPED, стр. 9-14. ACM, (2009)Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 20 (7): 1201-1210 (2012)BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs., , , , и . CICC, стр. 197-200. IEEE, (2000)A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation., , , , , , и . CICC, стр. 241-244. IEEE, (2003)Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling., , , и . ICICDT, стр. 1-4. IEEE, (2016)Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications., , , , , и . SoCC, стр. 339-344. IEEE, (2015)