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Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling.

, , , and . ICICDT, page 1-4. IEEE, (2016)

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Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness., , , , , and . ISCAS, page 2325-2328. IEEE, (2015)Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell., , , , and . ISLPED, page 255-258. ACM, (2014)A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance., , , , , , and . ESSDERC, page 157-160. IEEE, (2012)A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , and 9 other author(s). SoCC, page 197-200. IEEE, (2011)Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits., , , , , and . ICICDT, page 61-64. IEEE, (2013)Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source., , , , , , and . ICICDT, page 1-4. IEEE, (2012)Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices., , , , , and . ICICDT, page 1-4. IEEE, (2015)A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits., , , , , , and . APCCAS, page 463-466. IEEE, (2012)Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations., , , , and . ISCAS, page 1-4. IEEE, (2017)Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits., , , , , and . Microelectron. Reliab., 54 (4): 698-711 (2014)