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Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience.

, , , , , , , , and . Int. J. Embed. Real Time Commun. Syst., 3 (4): 1-18 (2012)

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Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design., , , and . Int. J. Embed. Real Time Commun. Syst., 2 (4): 1-20 (2011)Optimizing built-in pseudo-random self-testing for network-on-chip switches., , and . INA-OCMC@HiPEAC, page 21-24. ACM, (2012)Ultra-low latency NoC testing via pseudo-random test pattern compaction., , , , and . ISSoC, page 1-6. IEEE, (2012)Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs., , , , and . DATE, page 679-684. IEEE Computer Society, (2010)A library of dual-clock FIFOs for cost-effective and flexible MPSoC design., , and . ICSAMOS, page 20-27. IEEE, (2010)OSR-Lite: Fast and deadlock-free NoC reconfiguration framework., , , , , and . ICSAMOS, page 86-95. IEEE, (2012)An efficient, low-cost routing framework for convex mesh partitions to support virtualization., , , , and . ACM Trans. Embed. Comput. Syst., 12 (4): 107:1-107:24 (2013)Enabling power efficiency through dynamic rerouting on-chip., , , , , and . ACM Trans. Embed. Comput. Syst., 12 (4): 111:1-111:23 (2013)A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs., , , , , , , , and . ACM Trans. Embed. Comput. Syst., 12 (4): 106:1-106:29 (2013)Quest for the ultimate network-on-chip: the NaNoC project., , , , , , , , and . INA-OCMC@HiPEAC, page 43-46. ACM, (2012)