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A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling., , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 301-310. Springer, (2004)Quest for the ultimate network-on-chip: the NaNoC project., , , , , , , , and . INA-OCMC@HiPEAC, page 43-46. ACM, (2012)A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip., , , and . DSD, page 641-648. IEEE Computer Society, (2006)A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies., , , , , and . ASP-DAC, page 337-342. IEEE, (2014)Hardware compilation of application-specific memory-access interconnect., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (5): 756-771 (2006)A survey of research and practices of Network-on-chip., and . ACM Comput. Surv., 38 (1): 1 (2006)SOMA: a tool for synthesizing and optimizing memory accesses in ASICs., , , and . CODES+ISSS, page 231-236. ACM, (2005)An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip., , , and . SoC, page 171-174. IEEE, (2005)A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip., and . DATE, page 1226-1231. IEEE Computer Society, (2005)A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method., , and . DATE, page 648-653. EDA Consortium, San Jose, CA, USA, (2007)