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Disambiguation of "Chou, Adam"

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6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.

, , , , , , , , , , , , , , , , , , , , and . ISSCC, page 116-118. IEEE, (2020)

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Remi Chou

Joseph Chou

Maria Chou

Mike Chou

Hsin Chou

 

Other publications of authors with the same name

6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET., , , , , , , , , and 7 other author(s). ISSCC, page 114-115. IEEE, (2017)A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET., , , , , , , , , and 7 other author(s). VLSI Circuits, page 145-146. IEEE, (2018)6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET., , , , , , , , , and 11 other author(s). ISSCC, page 116-118. IEEE, (2020)A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (12): 3486-3502 (2017)A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies., , , , , , , , , and 7 other author(s). ISSCC, page 204-205. IEEE, (2023)A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 56 (1): 7-18 (2021)A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (4): 814-827 (2015)A 40-Gb/s serial link transceiver in 28-nm CMOS technology., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)