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6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.

J. Im, K. Zheng, A. Chou, L. Zhou, J. Kim, S. Chen, Y. Wang, H. Hung, K. Tan, W. Lin, A. Roldan, D. Carey, I. Chlis, R. Casey, A. Bekele, Y. Cao, D. Mahashin, H. Ahn, H. Zhang, Y. Frans, and K. Chang. ISSCC, page 116-118. IEEE, (2020)

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Lin Lin

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A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET.M. Erett, J. Hudner, D. Carey, R. Casey, K. Geary, K. Hearne, P. Neto, T. Mallard, V. Sooden, M. Smyth and 7 other author(s). IEEE J. Solid State Circuits, 52 (7): 1783-1797 (2017)3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET.Y. Frans, S. McLeod, H. Hedayati, M. Elzeftawi, J. Namkoong, W. Lin, J. Im, P. Upadhyaya, and K. Chang. ISSCC, page 68-70. IEEE, (2016)A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET.M. Erett, J. Hudner, D. Carey, R. Casey, K. Geary, K. Hearne, P. Neto, T. Mallard, V. Sooden, M. Smyth and 7 other author(s). ESSCIRC, page 297-300. IEEE, (2016)A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.J. Im, S. Chen, D. Freitas, A. Chou, L. Zhou, I. Zhuang, T. Cronin, D. Mahashin, W. Lin, K. Chan and 7 other author(s). VLSI Circuits, page 145-146. IEEE, (2018)6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.J. Im, K. Zheng, A. Chou, L. Zhou, J. Kim, S. Chen, Y. Wang, H. Hung, K. Tan, W. Lin and 11 other author(s). ISSCC, page 116-118. IEEE, (2020)A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET.M. Erett, D. Carey, R. Casey, J. Hudner, K. Geary, T. Lee, M. Raj, H. Zhang, A. Roldan, H. Zhao and 9 other author(s). CICC, page 1-8. IEEE, (2019)A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.P. Upadhyaya, C. Poon, S. Lim, J. Cho, A. Roldan, W. Zhang, J. Namkoong, T. Pham, B. Xu, W. Lin and 6 other author(s). IEEE J. Solid State Circuits, 54 (1): 18-28 (2019)A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET.P. Upadhyaya, C. Poon, S. Lim, J. Cho, A. Roldan, W. Zhang, J. Namkoong, T. Pham, B. Xu, W. Lin and 6 other author(s). ISSCC, page 108-110. IEEE, (2018)A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies.M. Raj, C. Xie, A. Bekele, A. Chou, W. Zhang, Y. Cao, J. Kim, N. Narang, H. Zhao, Y. Wang and 7 other author(s). ISSCC, page 204-205. IEEE, (2023)A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET.Y. Frans, S. McLeod, H. Hedayati, M. Elzeftawi, J. Namkoong, W. Lin, J. Im, P. Upadhyaya, and K. Chang. IEEE J. Solid State Circuits, 51 (12): 3167-3177 (2016)

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Disambiguation of "Lin, Winson"

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6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.

Please choose a person to relate this publication to

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lin, Winson"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.

Please choose a person to relate this publication to

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

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6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.