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Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures.

, , , , and . NANOARCH, page 7-12. ACM, (2016)

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Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters., , , , , and . ISVLSI, page 18-23. IEEE, (2020)Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems., , , and . ICASSP, page 1549-1552. IEEE, (2020)RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM., , , , , , , and . SAMOS, volume 11733 of Lecture Notes in Computer Science, page 34-47. Springer, (2019)SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures., , , , and . NVMTS, page 1-4. IEEE, (2015)Functionality Enhanced Memories for Edge-AI Embedded Systems., , , , and . NVMTS, page 1-4. IEEE, (2019)Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference., , , , and . CoRR, (2022)A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs., , , , and . ISVLSI, page 164-169. IEEE, (2021)A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance., , , and . VLSI-SOC, page 94-99. IEEE, (2020)BLADE: A BitLine Accelerator for Devices on the Edge., , , , and . ACM Great Lakes Symposium on VLSI, page 207-212. ACM, (2019)Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge., , , , and . ACM Great Lakes Symposium on VLSI, page 249-254. ACM, (2022)