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Disambiguation of "Hara, Hiroyuki"

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7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.

, , , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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Hiroyuki Tan

Hiroyuki Kobayashi

Sayuri Hara

Takeshi Hara

Fumio Hara

 

Other publications of authors with the same name

Pulse-Width Modulation with Current Uniformization for TFT-OLEDs., , , , , , and . IEICE Trans. Electron., 90-C (11): 2076-2082 (2007)A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation., , , , and . IEICE Trans. Electron., 96-C (6): 894-902 (2013)Classification of Driving Methods for TFT-OLEDs and Novel Proposal Using Time Ratio Grayscale and Current Uniformization., , , , , and . IEICE Trans. Electron., 88-C (11): 2043-2050 (2005)A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm., , , , , , , , , and 4 other author(s). ISSCC, page 326-327. IEEE, (2010)A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS., , , and . ISSCC, page 338-340. IEEE, (2011)A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access., , , , , , , , , and 2 other author(s). A-SSCC, page 161-164. IEEE, (2011)Wireless and IP integrated system architectures for broadband mobile multimedia services., , , , , and . WCNC, page 593-597. IEEE, (1999)Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (12): 1379-1383 (2006)An automated runtime power-gating scheme., , , , , , , , and . ICCD, page 382-387. IEEE, (2007)An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation., , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2012)