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Disambiguation of "Ikegami, Kazutaka"

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7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.

, , , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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Ken'ichiro Ikegami

 

Other publications of authors with the same name

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications., , , and . VLSI Circuits, page 278-. IEEE, (2019)Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures., , , , , and . ISIC, page 316-319. IEEE, (2014)7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme., , , , , , , , , and 3 other author(s). ISSCC, page 132-133. IEEE, (2016)Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation., , , , , and . IPDPS Workshops, page 213-220. IEEE Computer Society, (2012)1200μm2 Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application., , , , , and . ISSCC, page 414-415. IEEE, (2008)Novel memory hierarchy with e-STT-MRAM for near-future applications., , , , , and . VLSI-DAT, page 1-2. IEEE, (2017)Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU., , , , , and . VLSIC, page 1-2. IEEE, (2014)High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only)., , , , , , and . FPGA, page 291. ACM, (2010)