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A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS.

, , , , , , and . IEEE J. Solid State Circuits, 49 (4): 917-927 (2014)

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20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 336-337. IEEE, (2017)Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS., , , , , and . CICC, page 1-4. IEEE, (2014)Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating., , , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 50-63 (2017)An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and $V_MIN$ Optimization., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 54 (1): 144-157 (2019)A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 57 (1): 6-20 (2022)A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS., , , , , , , , , and . CICC, page 1-4. IEEE, (2015)8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation., , , , , , , , , and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)A New Power-Consumption Optimization Technique for Two-Stage Operational Amplifiers., , , , , and . IEICE Trans. Electron., 94-C (6): 1138-1140 (2011)A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS., , , , , , and . IEEE J. Solid State Circuits, 49 (4): 917-927 (2014)A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (4): 701-705 (2011)