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Disambiguation of "Sano, Toru"

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A near-future prediction method for low power consumption on a many-core processor.

, , , , , , , , , , , and . DATE, page 1058-1059. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Toru Nomura

Toru Matsuyama

Toru Kashima

Kazuhiko Sano

Richard Heinrich Torunsky

 

Other publications of authors with the same name

A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications., , , , , , , , , and . VLSIC, page 150-151. IEEE, (2012)Instruction buffer mode for multi-context Dynamically Reconfigurable Processors., , , , and . FPL, page 215-220. IEEE, (2008)18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications., , , , , , , , , and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications., , , , , , , , , and 7 other author(s). ISSCC, page 132-134. IEEE, (2019)Development of low power many-core SoC for multimedia applications., , , , , and . DATE, page 773-777. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors., , , and . FPL, page 530-533. IEEE, (2009)A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array., , , , , and . ERSA, page 283-286. CSREA Press, (2009)Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors., , and . ERSA, page 112-118. CSREA Press, (2009)An evaluation of an energy efficient many-core SoC with parallelized face detection., , , , and . ASP-DAC, page 311-316. IEEE, (2014)MuCCRA-3: a low power dynamically reconfigurable processor array., , , , , , and . ASP-DAC, page 377-378. IEEE, (2010)