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A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 55 (4): 945-955 (2020)Investigating biocomplexity through the agent-based paradigm., и . Briefings Bioinform., 16 (1): 137-152 (2015)Future Performance Challenges in Nanometer Design., и . DAC, стр. 3-8. ACM, (2001)16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS., , , , , , , , , и . ISSCC, стр. 276-277. IEEE, (2014)A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array., , , , , , , , , и 2 other автор(ы). VLSI Circuits, стр. 238-. IEEE, (2019)A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures., , , , , , , , и . VLSI Circuits, стр. 1-2. IEEE, (2020)A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS., , , , , , , , , и 1 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2020)Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators., , , , и . ARITH, стр. 84-87. IEEE, (2019)A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS., , , , , , , и . ESSCIRC, стр. 98-101. IEEE, (2018)μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS., , , , , , , , , и 1 other автор(ы). ESSCIRC, стр. 116-119. IEEE, (2015)