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Disambiguation of "Kaul, Himanshu"

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A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.

, , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 59-67 (2015)

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Himanshu Raj

Himanshu Verma

Himanshu Tyagi

Himanshu Ghildiyal

Himanshu Patel

 

Other publications of authors with the same name

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 59-67 (2015)A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)Power-aware global signaling strategies., , , , , and . ISCAS (1), page 604-607. IEEE, (2005)DVS for On-Chip Bus Designs Based on Timing Error Correction, , , , and . CoRR, (2007)High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS.. SoCC, page 324. IEEE, (2005)Active shielding of RLC global interconnects., , and . Timing Issues in the Specification and Synthesis of Digital Systems, page 98-104. ACM, (2002)A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS., , , , and . ESSCIRC, page 182-185. IEEE, (2008)Clock net optimization using active shielding., , and . ESSCIRC, page 265-268. IEEE, (2003)16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS., , , , , , , , , and . ISSCC, page 278-279. IEEE, (2014)DVS for On-Chip Bus Designs Based on Timing Error Correction., , , , and . DATE, page 80-85. IEEE Computer Society, (2005)