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Disambiguation of "Tokunaga, Carlos"

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Design for test and reliability in ultimate CMOS.

, , , , , , , , , , , , , and . DATE, page 677-682. IEEE, (2012)

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Yasno Tokunaga

Yasuo Tokunaga

Carlos Briede

Carlos Rodríguez

Carlos Schleipen

 

Other publications of authors with the same name

True Random Number Generator With a Metastability-Based Quality Control., , and . IEEE J. Solid State Circuits, 43 (1): 78-85 (2008)Securing Encryption Systems With a Switched Capacitor Current Equalizer., and . IEEE J. Solid State Circuits, 45 (1): 23-31 (2010)8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation., , , , , , , , , and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)A fully integrated charge sharing active decap scheme for power supply noise suppression., , , , , and . SoCC, page 374-379. IEEE, (2015)Resilient microprocessor design for high performance & energy efficiency., , , , , , , , , and 1 other author(s). ISLPED, page 355-356. ACM, (2010)An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS., , , and . IEEE J. Solid State Circuits, 58 (4): 1117-1128 (2023)Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 51 (1): 18-30 (2016)A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 48 (8): 1963-1969 (2013)CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation., , , , , , and . A-SSCC, page 1-3. IEEE, (2021)Resilient design in scaled CMOS for energy efficiency., , , , , , , , , and 2 other author(s). ASP-DAC, page 625. IEEE, (2010)