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Design, implementation, and verification of active cache emulator (ACE)., , and . FPGA, page 63-72. ACM, (2006)Trading Off Cache Capacity for Low-Voltage Operation., , , , , and . IEEE Micro, 29 (1): 96-103 (2009)O2MD²: A New Post-Quantum Cryptosystem With One-to-Many Distributed Key Management Based on Prime Modulo Double Encapsulation., , , and . IEEE Access, (2021)Adaptive Cache Design to Enable Reliable Low-Voltage Operation., , , , and . IEEE Trans. Computers, 60 (1): 50-63 (2011)A Reliable, Low-Cost, Low-Energy Physically Unclonable Function Circuit Through Effective Filtering., , , , , and . VLSI-DAT, page 1-4. IEEE, (2019)CompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator Arrays., , , , , and . A-SSCC, page 1-4. IEEE, (2020)Reducing cache and TLB power by exploiting memory region and privilege level semantics., , , , , , and . J. Syst. Archit., 59 (6): 279-295 (2013)Advances of the Counterflow Pipeline Microarchitecture., , and . HPCA, page 230-236. IEEE Computer Society, (1997)Distributed hardware matcher framework for SoC survivability., and . DATE, page 305-310. IEEE, (2011)Design for test and reliability in ultimate CMOS., , , , , , , , , and 4 other author(s). DATE, page 677-682. IEEE, (2012)