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Accelerating Synchronization Using Moving Compute to Data Model at 1, 000-core Multicore Scale.

, , , and . ACM Trans. Archit. Code Optim., 16 (1): 4:1-4:27 (2019)

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A model to exploit power-performance efficiency in superscalar processors via structure resizing., and . ACM Great Lakes Symposium on VLSI, page 215-220. ACM, (2010)Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines., and . HiPEAC, volume 5409 of Lecture Notes in Computer Science, page 293-307. Springer, (2009)A framework to accelerate sequential programs on homogeneous multicores., , , and . VLSI-SoC, page 344-347. IEEE, (2013)POSTER: Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-Parallel Algorithms., , , and . PACT, page 495-496. IEEE, (2019)A self-adaptive system architecture to address transistor aging., and . DATE, page 81-86. IEEE, (2009)In-Hardware Moving Compute to Data Model to Accelerate Thread Synchronization on Large Multicores., , , and . IEEE Micro, 40 (1): 83-92 (2020)SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors., and . IEEE Comput. Archit. Lett., 21 (2): 129-132 (July 2022)Hardware Root-of-Trust implementations in Trusted Execution Environments., , , , and . IACR Cryptol. ePrint Arch., (2023)ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes., , , and . ACM Trans. Archit. Code Optim., 20 (3): 32:1-32:24 (September 2023)MaxK-GNN: Towards Theoretical Speed Limits for Accelerating Graph Neural Networks Training., , , , , , , , and . CoRR, (2023)