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An Improved Design of a Reversible Fault Tolerant LUT-based FPGA.

, , and . VLSID, page 445-450. IEEE Computer Society, (2016)

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An Efficient Design of a Reversible Barrel Shifter., and . VLSI Design, page 93-98. IEEE Computer Society, (2010)Synthesis of Full-Adder Circuit Using Reversible Logic., , , and . VLSI Design, page 757-760. IEEE Computer Society, (2004)Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder., and . VLSI Design, page 255-260. IEEE Computer Society, (2005)A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic., , , and . Asian Test Symposium, page 90-95. IEEE Computer Society, (2003)An efficient design technique of a quantum divider circuit., , and . ISCAS, page 2102-2105. IEEE, (2016)An efficient approach for designing and minimizing reversible programmable logic arrays., , , and . ACM Great Lakes Symposium on VLSI, page 215-220. ACM, (2012)Khulna-9208, Bangladesh** Department of Computer Science, University of Dhaka Dhaka-1000, Bangladesh, , , and . Proceedings, International Conference on Computer and Information Technology, December 28-29, 2001, 32, page 62. Department of Computer Science, University of Dhaka, (2001)A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits., , , and . ISMVL, page 111-116. IEEE Computer Society, (2003)A novel approach to perform reversible addition/subtraction operations using deoxyribonucleic acid., , and . ISCAS, page 1828-1831. IEEE, (2014)A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array., , and . VLSI Design, page 311-316. IEEE Computer Society, (2006)