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Disambiguation of "Liu, Ren-Shuo"

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Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors.

, , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 55 (1): 203-215 (2020)

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Shuo Liu

Shuo Li

Shuo Wang

Shuo Bai

Shuo Zhang

 

Other publications of authors with the same name

A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array., , , , , , , , , and 2 other author(s). BioCAS, page 1-4. IEEE, (2018)Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators., , and . ASP-DAC, page 242-247. ACM, (2021)Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference., and . DAC, page 1-6. IEEE, (2023)Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture., and . DAC, page 1-6. IEEE, (2023)Block and Subword-Scaling Floating-Point (BSFP) : An Efficient Non-Uniform Quantization For Low Precision Inference., , and . ICLR, OpenReview.net, (2023)8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips., , , , , , , , , and 11 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (April 2024)A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel., , , , , , , , and . IEEE J. Solid State Circuits, 56 (8): 2516-2524 (2021)A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 55 (1): 189-202 (2020)A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 55 (10): 2790-2801 (2020)Bucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs., and . MICRO, page 1002-1015. ACM, (2023)