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Disambiguation of "Chakrabarti, Chaitali"

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Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.

, , , , , , , , , , , , and . IEEE J. Solid State Circuits, 57 (4): 986-998 (2022)

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Chaitali Chakrabarti

Subhadip Chakrabarti

Gopa Chakrabarti

Romon Chakrabarti

Sudhir Kumar Chakrabarti

 

Other publications of authors with the same name

Articulation constrained learning with application to speech emotion recognition., , , , and . EURASIP J. Audio Speech Music. Process., (2019)Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (4): 986-998 (2022)High sample rate array architectures for median filters.. IEEE Trans. Signal Process., 42 (3): 707-712 (1994)Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression., , , , , and . CoRR, (2018)A low power scheduling scheme with resources operating at multiple voltages., and . IEEE Trans. Very Large Scale Integr. Syst., 10 (1): 6-14 (2002)Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks., , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 34:1-34:22 (2022)Automated Parallel Kernel Extraction from Dynamic Application Traces., , and . CoRR, (2020)Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks., , , , , and . CoRR, (2021)Deep Learning for Moving Blockage Prediction using Real Millimeter Wave Measurements., , , , and . CoRR, (2021)T-BFA: Targeted Bit-Flip Adversarial Weight Attack., , , , , and . IEEE Trans. Pattern Anal. Mach. Intell., 44 (11): 7928-7939 (2022)