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Disambiguation of "Ryu, Seung-Tak"

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A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC.

, , , and . VLSI Circuits, page 72-. IEEE, (2019)

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Seung-Hun Ryu

Seung-Min Ryu

Jung-Hun Seung

Ryu Yoshiwhara

Hosuk Ryu

 

Other publications of authors with the same name

A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm2., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 794-798 (2016)A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (6): 518-522 (2016)A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (9): 1154-1158 (2018)A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme., , , and . IEEE J. Solid State Circuits, 53 (9): 2584-2594 (2018)A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 54 (9): 2532-2542 (2019)Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference., , , , and . IEEE J. Solid State Circuits, 52 (12): 3115-3118 (2017)A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation., , , , and . IEEE J. Solid State Circuits, 50 (10): 2319-2330 (2015)A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration., , , , and . VLSI Circuits, page 138-. IEEE, (2019)A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction., , , , and . IEEE J. Solid State Circuits, 52 (9): 2488-2497 (2017)A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability., , , , and . IEEE J. Solid State Circuits, 55 (10): 2660-2669 (2020)