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Disambiguation of "Seo, Min-Jae"

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A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC.

, , , and . VLSI Circuits, page 72-. IEEE, (2019)

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Min-Soon Seo

Jae-Min Kim

Jae-Min Lee

Jae-Min Lee

Min-Jae Kwon

 

Other publications of authors with the same name

A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers., , , , , , , , and . IEEE J. Solid State Circuits, 54 (6): 1812-1823 (2019)A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (3): 281-285 (2018)A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique., , and . IEEE J. Solid State Circuits, 57 (9): 2791-2801 (2022)A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (4): 610-614 (2020)A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC., , , , , , , , and . IEEE J. Solid State Circuits, 51 (8): 1826-1839 (2016)A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS., , , , and . ESSCIRC, page 323-326. IEEE, (2015)A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling., , , , , , , , and . IEEE J. Solid State Circuits, 53 (4): 1139-1148 (2018)A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (11): 3617-3627 (2018)A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (12): 1904-1908 (2018)Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (2): 322-332 (2017)