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Disambiguation of "Hijaz, Farrukh"

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Locality-aware data replication in the last-level cache for large scale multicores.

, , , , and . J. Supercomput., 72 (2): 718-752 (2016)

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Omar Farrukh

Sameh Hijazi

Isam Hijazi

Muaz Hijazin

Mohammed Hijazi

 

Other publications of authors with the same name

ARBench: Augmented Reality Benchmark For Mobile Devices., , , , , and . ISPASS, page 242-244. IEEE, (2022)A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages., , and . ICCD, page 85-92. IEEE Computer Society, (2013)NUCA-L1: A Non-Uniform Access Latency Level-1 Cache Architecture for Multicores Operating at Near-Threshold Voltages., and . ACM Trans. Archit. Code Optim., 11 (3): 29:1-29:28 (2014)M-MAP: Multi-factor memory authentication for secure embedded processors., , , , , , , and . ICCD, page 471-474. IEEE Computer Society, (2015)Exploring the performance implications of memory safety primitives in many-core processors executing multi-threaded workloads., , , , and . HASP@ISCA, page 6:1-6:8. ACM, (2015)Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging., , , , , and . IPDPS, page 254-264. IEEE Computer Society, (2017)Towards efficient dynamic data placement in NoC-based multicores., , and . ICCD, page 369-376. IEEE Computer Society, (2013)Low-Latency Mechanisms for Near-Threshold Operation of Private Caches in Shared Memory Multicores., , and . MICRO Workshops, page 68-73. IEEE Computer Society, (2012)CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores., , , and . IISWC, page 44-55. IEEE Computer Society, (2015)Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication., , , and . NAS, page 122-129. IEEE Computer Society, (2015)