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Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication.

, , , and . NAS, page 122-129. IEEE Computer Society, (2015)

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MINIME-validator: Validating hardware with synthetic parallel testcases., , and . DATE, page 386-391. IEEE, (2017)Functional Validation of a New Network Switch Architecture Using Rapid Prototyping Techniques., and . MTV, page 3-7. IEEE Computer Society, (2013)Using software architectural patterns for synthetic embedded multicore benchmark development., , , and . IISWC, page 89-99. IEEE Computer Society, (2012)Stream synthesis for a wormhole run-time reconfigurable platform., and . FPL, volume 1304 of Lecture Notes in Computer Science, page 101-110. Springer, (1997)MBET: Resilience Improvement Method for DNNs., , , and . AITest, page 72-78. IEEE, (2022)Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging., , , , , and . IPDPS, page 254-264. IEEE Computer Society, (2017)Retiming Verification Using Sequential Equivalence Checking., and . MTV, page 138-142. IEEE Computer Society, (2005)Simulated Quantization, Real Power Savings., , , , , , and . CVPR Workshops, page 2756-2760. IEEE, (2022)Multicore Resource Isolation for Deterministic, Resilient and Secure Concurrent Execution of Safety-Critical Applications., , , and . IEEE Comput. Archit. Lett., 17 (2): 230-234 (2018)An Introduction to the Plasma Language., , , and . MTV, page 12-22. IEEE Computer Society, (2005)