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Disambiguation of "Weber, Serge"

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FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding.

, , , , and . SoCC, page 423-426. IEEE, (2009)

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Elena Sergeyev

Nikolai Sergeev

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Dieter Sergel

Jean-Frédéric Sergejew

 

Other publications of authors with the same name

Parallel architecture dedicated to connected component analysis., , , and . ICPR, page 699-703. IEEE Computer Society, (1996)The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation., , , and . J. Univers. Comput. Sci., 13 (3): 349-362 (2007)FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding., , , , and . SoCC, page 423-426. IEEE, (2009)An approach: FPGA based dynamically reconfigurable architecture to enable several scheme controls for power converters., , and . CCE, page 1-6. IEEE, (2012)Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC., , and . DELTA, page 153-157. IEEE Computer Society, (2008)High performance scalable hardware SOM architecture for real-time vector quantization., , and . IPAS, page 256-261. IEEE, (2018)Scalable, dynamic and growing hardware self-organizing architecture for real-time vector quantization., , , , and . ICECS, page 1-4. IEEE, (2020)A Multi-Application, Scalable and Adaptable Hardware SOM Architecture., , , , and . IJCNN, page 1-8. IEEE, (2019)Cluster-Based Hybrid Reconfigurable Architecture for Auto-adaptive SoC., , and . ICECS, page 979-982. IEEE, (2007)Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design., , , and . IPDPS, page 178. IEEE Computer Society, (2003)