( en | de | ru )

 

Disambiguation of "Park, Byung-Gook"

Author of the publication

copydeleteadd this publication to your clipboard
4-bit Multilevel Operation in Overshoot Suppressed Al2O3/TiOx Resistive Random-Access Memory Crossbar Array.

, , , , , , and . Adv. Intell. Syst., (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sung Gook Park

Byung-Hoon Park

Ky Byung Park

Byung-Wook Park

Byung-Nam Park

 

Other publications of authors with the same name

Hardware-Based Spiking Neural Network Using a TFT-Type AND Flash Memory Array Architecture Based on Direct Feedback Alignment., , , , , , , and . IEEE Access, (2021)Synchronous mirror delay for multiphase locking., , , , , , and . IEEE J. Solid State Circuits, 39 (1): 150-156 (2004)L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications., , , , , , and . IEICE Trans. Electron., 96-C (5): 634-638 (2013)Ultrasensitive Electrical Detection of Hemagglutinin for Point-of-Care Detection of Influenza Virus Based on a CMP-NANA Probe and Top-Down Processed Silicon Nanowire Field-Effect Transistors., , , , , , , , , and 1 other author(s). Sensors, 19 (20): 4502 (2019)On-chip trainable hardware-based deep Q-networks approximating a backpropagation algorithm., , , , , , , , , and . Neural Comput. Appl., 33 (15): 9391-9402 (2021)Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)., , , , , , , and . IEICE Trans. Electron., 91-C (5): 731-735 (2008)Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory., , , , , and . IEICE Trans. Electron., 92-C (5): 659-663 (2009)Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices., , , , , , , and . IEICE Trans. Electron., 90-C (5): 988-993 (2007)Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)., , , , , and . IEICE Trans. Electron., 92-C (5): 620-626 (2009)Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering., , , , , , , , , and 4 other author(s). IEEE Access, (2020)