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Disambiguation of "Cheng, Yuanqing"

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PDG: A Prefetcher for Dynamic Graph Updating.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1246-1259 (April 2024)

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Yuanqing Gao

Yuanqing Guo

Cheng-Yung Cheng

Ying Min Cheng

I-Fen Cheng

 

Other publications of authors with the same name

Architecture design with STT-RAM: Opportunities and challenges., , , , , and . ASP-DAC, page 109-114. IEEE, (2016)DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache., , , , and . ISQED, page 408-414. IEEE, (2020)A Survey of Test and Reliability Solutions for Magnetic Random Access Memories., , , , , and . Proc. IEEE, 109 (2): 149-169 (2021)Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization., , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 16 (3): 29:1-29:18 (2020)All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits., , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (4): 71:1-71:20 (2022)ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY., , , , and . ICCAD, page 118. ACM, (2016)TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning., , , , , , and . DAC, page 1-6. IEEE, (2023)Quantitative evaluation of reliability and performance for STT-MRAM., , , , , , and . ISCAS, page 1150-1153. IEEE, (2016)A body-biasing of readout circuit for STT-RAM with improved thermal reliability., , , , , and . ISCAS, page 1530-1533. IEEE, (2015)A Study of 3-D Power Delivery Networks With Multiple Clock Domains., and . IEEE Trans. Very Large Scale Integr. Syst., 24 (11): 3218-3231 (2016)