( en | de | ru )

 

Disambiguation of "Reorda, Matteo Sonza"

Author of the publication

copydeleteadd this publication to your clipboard
Cumulative embedded memory failure bitmap display & analysis.

, , , , , , , and . DDECS, page 255-260. IEEE Computer Society, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Matteo Garavoglia

Matteo Rini

Marco Matteo

Matteo Gabba

Matteo Bertini

 

Other publications of authors with the same name

An experimental analysis of the effectiveness of the circular self-test path technique., , and . EURO-DAC, page 246-251. IEEE Computer Society, (1994)BASTION: Board and SoC test instrumentation for ageing and no failure found., , , , , , , , and . DATE, page 115-120. IEEE, (2017)Test-Plan Optimization for Flying-Probes In-Circuit Testers., , , and . ITC-Asia, page 19-24. IEEE, (2019)Software-Based Self-Test for Transition Faults: a Case Study., , , and . VLSI-SoC, page 76-81. IEEE, (2019)A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks., , , and . IEEE Trans. Computers, 69 (1): 87-98 (2020)New techniques for efficiently assessing reliability of SOCs., , , , and . Microelectron. J., 34 (1): 53-61 (2003)On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 813-823 (2014)RT-Level ITC'99 Benchmarks and First ATPG Results., , and . IEEE Des. Test Comput., 17 (3): 44-53 (2000)System-level test bench generation in a co-design framework., , , , and . ETW, page 25-30. IEEE Computer Society, (2000)Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs., , , , and . J. Electron. Test., 23 (1): 47-54 (2007)