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A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (3): 672-684 (2019)A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects., , and . IEEE J. Solid State Circuits, 43 (5): 1235-1246 (2008)Analog Solutions of Discrete Markov Chains via Memristor Crossbars., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (12): 4910-4923 (2021)3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS., , , , , and . ISSCC, page 1-3. IEEE, (2015)Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture : (Invited Special Session Paper)., , , and . MWSCAS, page 1151-1154. IEEE, (2019)Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS., , , and . CICC, page 1-4. IEEE, (2011)A 0.18-μm CMOS fully integrated 0.7-6 GHz PLL-based complex dielectric spectroscopy system., , , , and . CICC, page 1-4. IEEE, (2014)A 20 Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter., , and . Microelectron. J., 43 (10): 687-696 (2012)Power Efficiency Comparisons of Interchip Optical Interconnect Architectures., and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (5): 343-347 (2010)A Wide-Band Fully-Integrated CMOS Ring-Oscillator PLL-Based Complex Dielectric Spectroscopy System., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 1940-1949 (2015)