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Disambiguation of "Fan, Yang-Hang"

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A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS.

, , , , , , , , , and . IEEE J. Solid State Circuits, 54 (3): 672-684 (2019)

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Fan Yang

Fan Yang

Fan Yang

Fan Yang

Fan Yang

 

Other publications of authors with the same name

A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS., , , , , , and . CICC, page 1-4. IEEE, (2019)A 22 Gb/s Directly Modulated Optical Injection-Locked Quantum-Dot Microring Laser Transmitter with Integrated CMOS Driver., , , , , , , , , and . ISCAS, page 1-4. IEEE, (2020)A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS., , , , , , and . CICC, page 1-4. IEEE, (2020)A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS., , , , , , , , , and . CICC, page 1-4. IEEE, (2018)A Direct Bond Interconnect 3D Co-Integrated Silicon-Photonic Transceiver in 12nm FinFET with -20.3dBm OMA Sensitivity and 691fJ/bit., , , , , , , , , and 6 other author(s). OFC, page 1-3. IEEE, (2023)A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques., , , , , , and . IEEE J. Solid State Circuits, 55 (2): 439-451 (2020)An integrated system for brain machine interface., , , , , , , , and . Healthcom, page 407-410. IEEE, (2012)A 12.5 Gb/s 1.38 mW Inverter-Based Optical Receiver in 28 nm CMOS., , , , , , , , , and . MWSCAS, page 1-4. IEEE, (2022)A Directly Modulated Quantum Dot Microring Laser Transmitter with Integrated CMOS Driver., , , , , , , and . OFC, page 1-3. IEEE, (2019)A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (3): 672-684 (2019)