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Disambiguation of "Hwang, Sewook"

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29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.

, , , , , , and . ISSCC, page 490-491. IEEE, (2017)

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Hak Hwang

Sungil Hwang

Byung Kook Hwang

Kyung-Yub Hwang

Giin-Tarng Hwang

 

Other publications of authors with the same name

An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface., , , , , , , and . ISSCC, page 312-313. IEEE, (2013)A 0.076mm2 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS., , , , and . ISSCC, page 360-362. IEEE, (2011)17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces., , , , and . ISSCC, page 1-3. IEEE, (2015)A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (6): 650-654 (2017)A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS., , , and . ISCAS, page 1959-1962. IEEE, (2012)A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 344-353 (2017)34.1 An 8960-Element Ultrasound-on-Chip for Point-of-Care Ultrasound., , , , , , , , , and 7 other author(s). ISSCC, page 480-482. IEEE, (2021)A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (2): 303-313 (2013)A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2691-2702 (2017)29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces., , , , , , and . ISSCC, page 490-491. IEEE, (2017)