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ZCOMP: Reducing DNN Cross-Layer Memory Footprint Using Vector Extensions., , and . MICRO, page 126-138. ACM, (2019)FFTs with Near-Optimal Memory Access Through Block Data Layouts: Algorithm, Architecture and Design Automation., , and . J. Signal Process. Syst., 85 (1): 67-82 (2016)MobileDets: Searching for Object Detection Architectures for Mobile Accelerators., , , , , , , , and . CoRR, (2020)Enabling portable energy efficiency with memory accelerated library., , , , , , and . MICRO, page 750-761. ACM, (2015)Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models., , , , , , , and . CoRR, (2021)Apollo: Transferable Architecture Exploration., , , , , , , , , and . CoRR, (2021)An Evaluation of Edge TPU Accelerators for Convolutional Neural Networks., , , , and . CoRR, (2021)Data reorganization in memory using 3D-stacked DRAM., , and . ISCA, page 131-143. ACM, (2015)Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes., , , and . FCCM, page 188-191. IEEE Computer Society, (2012)Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only)., , , and . FPGA, page 271. ACM, (2012)