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Disambiguation of "Nedovic, Nikola"

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Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits.

, , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (10): 3038-3049 (2008)

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Nikola Schoofs

Nikola Stiasni

Nikola Lange

Nikola Schulenberg

Nikola Gaidzik

 

Other publications of authors with the same name

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 54 (1): 43-54 (2019)A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX., , , , , , , , , and . ISSCC, page 224-598. IEEE, (2007)A test circuit for measurement of clocked storage element characteristics., , and . IEEE J. Solid State Circuits, 39 (8): 1294-1304 (2004)Conditional pre-charge techniques for power-efficient dual-edge clocking., , and . ISLPED, page 56-59. ACM, (2002)A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers., , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 724-732. Springer, (2005)Timing Characterization of Dual-edge Triggered Flip-flops., , and . ICCD, page 538-541. IEEE Computer Society, (2001)Comparative analysis of double-edge versus single-edge triggered clocked storage elements., , and . ISCAS (5), page 105-108. IEEE, (2002)The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements., , and . IEEE J. Solid State Circuits, 42 (6): 1392-1404 (2007)Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (10): 3038-3049 (2008)Conditional techniques for low power consumption flip-flops., , and . ICECS, page 803-806. IEEE, (2001)