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Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage.

, , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (3): 844-853 (2015)

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Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme., , and . ASP-DAC, page 83-84. IEEE, (2013)Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths., , , and . IEICE Trans. Electron., 99-C (4): 444-451 (2016)Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory., , , , , , , and . IEEE J. Solid State Circuits, 51 (8): 1938-1951 (2016)95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm., , , , , and . ISSCC, page 204-206. IEEE, (2011)Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs)., , and . IEEE J. Solid State Circuits, 48 (11): 2920-2933 (2013)19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers., , , , and . ISSCC, page 336-337. IEEE, (2014)Improvement of Read Margin and Its Distribution by VTH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection., , , , and . IEEE J. Solid State Circuits, 46 (9): 2180-2188 (2011)7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage., , , , , and . ISSCC, page 1-3. IEEE, (2015)Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2208-2219 (2016)Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor., , , , and . IEICE Trans. Electron., 95-C (4): 564-571 (2012)