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pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.

Y. Kim, H. Kwon, S. Doo, Y. Eom, Y. Kim, M. Ahn, Y. Kim, S. Jung, S. Do, C. Lee, J. Kim, D. Kang, K. Park, J. Shin, J. Lee, S. Oh, S. Lee, J. Yu, J. Kwon, K. Yu, C. Jeon, S. Kim, M. Won, G. hee Cho, H. Park, H. Kim, J. Lee, S. Cho, K. Park, J. Park, Y. Lee, Y. Kim, Y. Seo, B. Cho, C. Shin, C. Lee, Y. Lee, Y. Song, S. Bang, Y. Park, S. Choi, B. Kim, G. Han, S. Bae, H. Kwon, J. Choi, Y. Sohn, K. Park, and S. Jang. ISSCC, page 204-206. IEEE, (2018)

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Yeon-Su Lee

Sang-Chun Yeon

Yeon Ha

Hermann Doose

Eva Doose

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A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.Y. Kim, H. Kwon, S. Doo, M. Ahn, Y. Kim, Y. Lee, D. Kang, S. Do, C. Lee, G. hee Cho and 29 other author(s). IEEE J. Solid State Circuits, 54 (1): 197-209 (2019)25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.T. Oh, H. Chung, Y. Cho, J. Ryu, K. Lee, C. Lee, J. Lee, H. Kim, M. Jang, G. Han and 16 other author(s). ISSCC, page 430-431. IEEE, (2014)A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.T. Oh, H. Chung, J. Park, K. Lee, S. Oh, S. Doo, H. Kim, C. Lee, H. Kim, J. Lee and 10 other author(s). IEEE J. Solid State Circuits, 50 (1): 178-190 (2015)23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.H. Kwon, E. Seo, C. Lee, Y. Seo, G. Han, H. Kim, J. Lee, M. Jang, S. Do, S. Cho and 26 other author(s). ISSCC, page 394-395. IEEE, (2017)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.H. Chi, C. Lee, J. Park, J. Heo, J. Jung, D. Lee, D. Kim, D. Park, K. Kim, S. Kim and 29 other author(s). ISSCC, page 382-384. IEEE, (2020)A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.Y. Kim, H. Kwon, S. Doo, Y. Eom, Y. Kim, M. Ahn, Y. Kim, S. Jung, S. Do, C. Lee and 39 other author(s). ISSCC, page 204-206. IEEE, (2018)A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.S. Bae, Y. Sohn, T. Oh, S. Kim, Y. Yang, D. Kim, S. Kwak, H. Seol, C. Shin, M. Park and 19 other author(s). ISSCC, page 498-500. IEEE, (2011)Dynamic Power Reduction of TCAM Using Selective Precharging of Match Lines.S. Doo, and K. Kwon. IEEE Big Data, page 6633-6635. IEEE, (2022)

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Disambiguation of "Doo, Su-Yeon"

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A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.

Please choose a person to relate this publication to

Yeon-Su Lee

Sang-Chun Yeon

Yeon Ha

Hermann Doose

Eva Doose

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Doo, Su-Yeon"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.

Please choose a person to relate this publication to

Yeon-Su Lee

Sang-Chun Yeon

Yeon Ha

Hermann Doose

Eva Doose

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.