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A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS.

, , , , , , and . IEEE J. Solid State Circuits, 55 (1): 19-26 (2020)

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Errata Erratum to Ä 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"., , , , , , and . IEEE J. Solid State Circuits, 55 (4): 1124 (2020)A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 58 (4): 1074-1086 (2023)40-Gb/s circuits built from a 120-GHz fT SiGe technology., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 37 (9): 1106-1114 (2002)Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits., , , and . Proc. IEEE, 88 (10): 1572-1582 (2000)29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET., , , , , , , , , and 6 other author(s). ISSCC, page 482-483. IEEE, (2017)Session 6 overview: Ultra-high-speed wireline: Wireline subcommittee., , and . ISSCC, page 100-101. IEEE, (2018)Introduction to the Special Section on the 2008 Compound Semiconductor Integrated Circuit Symposium (CSICS'08)., and . IEEE J. Solid State Circuits, 43 (10): 2175-2176 (2008)50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems., , and . IEEE J. Solid State Circuits, 37 (12): 1790-1794 (2002)A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration., , , , , , , , and . CICC, page 1-4. IEEE, (2015)Very high speed integrated circuits for optical communication., and . ICECS, page 189-192. IEEE, (1998)