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Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform.

, , , , , and . ASICON, page 1-4. IEEE, (2015)

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A BIST scheme for high-speed Gain Cell eDRAM., , , and . ASICON, page 244-247. IEEE, (2011)A 2Mb ReRAM with two bits error correction codes circuit for high reliability application., , , , , , and . ASICON, page 1-4. IEEE, (2013)3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance., , , and . Microelectron. J., (2017)Multilevel Storage in Phase-Change Memory., , , and . IEICE Trans. Electron., 90-C (3): 634-640 (2007)A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (4): 336-340 (2016)Novel 2T programmable element to improve density and performance of FPGA., , and . IEICE Electron. Express, 8 (7): 454-459 (2011)64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage., , , , and . IEICE Electron. Express, 9 (12): 1051-1056 (2012)Low-Power Variation-Tolerant Nonvolatile Lookup Table Design., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (3): 1174-1178 (2016)A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application., , , , and . ISCAS, page 1-4. IEEE, (2017)A low cost and high reliability true random number generator based on resistive random access memory., , , , , , , and . ASICON, page 1-4. IEEE, (2015)