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s serializer IC with SFI-5.2 interface in 65nm CMOS.

K. Kanda, H. Tamura, T. Yamamoto, S. Matsubara, M. Kibune, Y. Doi, T. Shibasaki, N. Tzartzanis, A. Kristensson, S. Parikh, S. Ide, Y. Tsunoda, T. Yamabana, M. Sugawara, N. Kuwata, T. Ikeuchi, J. Ogawa, and W. Walker. ISSCC, page 360-361. IEEE, (2009)

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Takuji Shimano

Takuji Kadowaki

Masaaki Yamamoto

Shelby Yamamoto

Kenji Yamamoto

Other publications of authors with the same name

Development of a semi self-contained wall climbing robot with scanning type suction cups.T. Yano, T. Suwa, M. Murakami, and T. Yamamoto. IROS, page 900-905. IEEE, (1997)Trends and Challenges in Optical Communications Front-End.Y. Greshishchev, T. Yamamoto, and N. Shanbhag. ISSCC, page 394-395. IEEE, (2008)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS.Y. Doi, T. Shibasaki, T. Danjo, W. Chaivipas, T. Hashida, H. Miyaoka, M. Hoshino, Y. Koyanagi, T. Yamamoto, S. Tsukamoto and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)SimpleZSL: Extremely Simple and Fast Zero-Shot Learning with Nearest Neighbor Classifiers.M. Hiromoto, H. Akima, T. Ishihara, and T. Yamamoto. IEICE Trans. Inf. Syst., 105-D (2): 396-405 (2022)A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS.O. Tyshchenko, A. Sheikholeslami, H. Tamura, Y. Tomita, H. Yamaguchi, M. Kibune, and T. Yamamoto. ISSCC, page 166-167. IEEE, (2010)22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI.Y. Chen, M. Kibune, A. Toda, A. Hayakawa, T. Akiyama, S. Sekiguchi, H. Ebe, N. Imaizumi, T. Akahoshi, S. Akiyama and 7 other author(s). ISSCC, page 1-3. IEEE, (2015)A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS.K. Takatsu, H. Tamura, T. Yamamoto, Y. Doi, K. Kanda, T. Shibasaki, and T. Kuroda. CICC, page 1-4. IEEE, (2010)Power Prediction for Sustainable HPC.S. Suzuki, M. Hiraoka, T. Shiraishi, E. Kreshpa, T. Yamamoto, H. Fukuda, S. Matsui, M. Fujisaki, and A. Uno. J. Inf. Process., (2021)A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.K. Kanda, H. Tamura, T. Yamamoto, S. Matsubara, M. Kibune, Y. Doi, T. Shibasaki, N. Tzartzanis, A. Kristensson, S. Parikh and 8 other author(s). ISSCC, page 360-361. IEEE, (2009)A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects.A. Hayakawa, M. Kibune, A. Toda, S. Tanaka, T. Simoyama, Y. Chen, T. Akiyama, S. Okumura, T. Baba, T. Akahoshi and 14 other author(s). OFC, page 1-3. IEEE, (2015)

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Disambiguation of "Yamamoto, Takuji"

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A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.

Please choose a person to relate this publication to

Takuji Shimano

Takuji Kadowaki

Masaaki Yamamoto

Shelby Yamamoto

Kenji Yamamoto

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yamamoto, Takuji"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.

Please choose a person to relate this publication to

Takuji Shimano

Takuji Kadowaki

Masaaki Yamamoto

Shelby Yamamoto

Kenji Yamamoto

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.