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Disambiguation of "Horton, Raymond R."

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Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology.

, , , , , , , , , , , , , , and . CICC, page 659-662. IEEE, (2005)

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Graham Horton

Graham Horton

Graham Horton

Graham Horton

Graham Horton

 

Other publications of authors with the same name

Active line repair for thin-film-transistor liquid crystal displays., , , , , , and . IBM J. Res. Dev., 42 (3): 445-458 (1998)Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection., , , , , , , , , and 10 other author(s). IBM J. Res. Dev., 49 (4-5): 725-754 (2005)3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections., , , , , , , , , and 3 other author(s). IBM J. Res. Dev., 52 (6): 611-622 (2008)Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology., , , , , , , , , and 5 other author(s). CICC, page 659-662. IEEE, (2005)Three-dimensional silicon integration., , , , , , , , , and 6 other author(s). IBM J. Res. Dev., 52 (6): 553-569 (2008)3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 41 (8): 1718-1725 (2006)3D chip stacking with C4 technology., , , , , , , , , and 4 other author(s). IBM J. Res. Dev., 52 (6): 599-609 (2008)A 10.5-in.-diagonal SXGA active-matrix display., , , , , , , , , and 18 other author(s). IBM J. Res. Dev., 42 (3): 427-444 (1998)