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Active load with cross-coupled bulk for high-gain high-CMRR nanometer CMOS differential stages.

, , and . I. J. Circuit Theory and Applications, 47 (10): 1700-1704 (2019)

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Active load with cross-coupled bulk for high-gain high-CMRR nanometer CMOS differential stages., , and . I. J. Circuit Theory and Applications, 47 (10): 1700-1704 (2019)Current output stage with improved CMRR., , and . ICECS, page 543-546. IEEE, (2003)A toolbox for the symbolic analysis and simulation of linear analog circuits., , and . SMACD, page 1-4. IEEE, (2017)High-speed CMOS unity-gain current amplifier., , and . Microelectron. J., 37 (10): 1086-1091 (2006)Analysis and evaluation of harmonic distortion in the tunnel diode oscillator., , and . ISCAS, IEEE, (2006)Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (5): 933-940 (2007)Advances in Reversed Nested Miller Compensation., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (7): 1459-1470 (2007)High-performance and simple CMOS interface circuit for differential capacitive sensors.. IEEE Trans. Circuits Syst. II Express Briefs, 52-II (6): 327-330 (2005)A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS., , , , , and . IEEE J. Solid State Circuits, 43 (6): 1403-1413 (2008)Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017., , , , , , , and . Integr., (2018)