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Massively Parallel Analog Computing: Ariadne's Thread Was Made of Memristors., , and . IEEE Trans. Emerg. Top. Comput., 6 (1): 145-155 (2018)Modeling Cycle-to-Cycle Variation in Memristors for In-Situ Unsupervised Trace-STDP Learning., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (2): 627-631 (February 2024)Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms., , , , and . ICECS, page 1-8. IEEE, (2023)eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex., , , , , , , and . J. Signal Process. Syst., 92 (11): 1323-1343 (2020)DRRA-based Reconfigurable Architecture for Mixed-Radix FFT., , , and . VLSID, page 25-30. IEEE, (2023)Alternative Architectures Toward Reliable Memristive Crossbar Memories., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 206-217 (2016)Clock tree generation by abutment in synchoros VLSI design., , , and . Microprocess. Microsystems, (2023)Regional Clock Tree Generation by Abutment in Synchoros VLSI Design., , , and . CoRR, (2019)Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex., , , and . DATE, page 685-688. IEEE, (2021)Synthesis of predictable global NoC by abutment in synchoros VLSI design., , and . NOCS, page 61-66. ACM, (2021)