( en | de | ru )

 

Disambiguation of "Dennard, Robert H."

Author of the publication

copydeleteadd this publication to your clipboard
Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions.

, , , , , and . Proc. IEEE, 87 (4): 668-678 (1999)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Robert H Baerent

Robert H Gassmann

Robert H P McGregor

H -H Kaatz

Florian H H Giesert

 

Other publications of authors with the same name

Iddq Testing for High Performance CMOS - The Next Ten Years., , , , and . ED&TC, page 578-583. IEEE Computer Society, (1996)Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions., , , , , and . Proc. IEEE, 87 (4): 668-678 (1999)Device scaling limits of Si MOSFETs and their application dependencies., , , , , and . Proc. IEEE, 89 (3): 259-288 (2001)Practical Strategies for Power-Efficient Computing Technologies., , , , , , , and . Proc. IEEE, 98 (2): 215-236 (2010)Challenges and future directions for the scaling of dynamic random-access memory (DRAM)., , , , , , and . IBM J. Res. Dev., 46 (2-3): 187-222 (2002)Silicon CMOS devices beyond scaling., , , , , , , , , and . IBM J. Res. Dev., 50 (4-5): 339-362 (2006)CMOS scaling for high performance and low power-the next ten years., , and . Proc. IEEE, 83 (4): 595-606 (1995)A novel dynamic memory cell with internal voltage gain., and . IEEE J. Solid State Circuits, 40 (4): 884-894 (2005)1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 35 (11): 1673-1679 (2000)CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications., , , , , , , , , and 4 other author(s). IBM J. Res. Dev., 39 (1-2): 229-244 (1995)