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PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments.

, , , and . ISPASS, page 139-140. IEEE, (2019)

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An analysis of on-chip interconnection networks for large-scale chip multiprocessors., , and . ACM Trans. Archit. Code Optim., 7 (1): 4:1-4:28 (2010)Reliable Hyperdimensional Reasoning on Unreliable Emerging Technologies., , , , , , , , and . ICCAD, page 1-9. IEEE, (2023)Extending Summation Precision for Network Reduction Operations., , , and . SBAC-PAD, page 41-48. IEEE Computer Society, (2013)Last Level Collective Hardware Prefetching For Data-Parallel Applications., and . HiPC, page 72-83. IEEE Computer Society, (2017)Collective memory transfers for multi-core chips., , , and . ICS, page 343-352. ACM, (2014)Router designs for elastic buffer on-chip networks., and . SC, ACM, (2009)Analyzing Resource Utilization in an HPC System: A Case Study of NERSC's Perlmutter., , , , and . ISC, volume 13948 of Lecture Notes in Computer Science, page 297-316. Springer, (2023)SpecLock: Speculative Lock Forwarding., , and . ICCD, page 273-282. IEEE, (2019)Elastic-buffer flow control for on-chip networks., , and . HPCA, page 151-162. IEEE Computer Society, (2009)Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies., , , , and . ISC Workshops, volume 10524 of Lecture Notes in Computer Science, page 115-123. Springer, (2017)