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Disambiguation of "Sakanushi, Keishi"

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Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.

, , , , , , and . ASP-DAC, page 449-454. IEEE, (2009)

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Other publications of authors with the same name

Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors., , , , , , and . ASP-DAC, page 449-454. IEEE, (2009)Enabling RTOS simulation modeling in a system level design language., , , and . ASP-DAC, page 936-939. ACM Press, (2005)Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation., , , , and . ICDCS Workshops, page 824-830. IEEE Computer Society, (2004)A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units., , , , and . ASP-DAC, page 286-291. IEEE Computer Society, (2007)RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC., , , and . DATE, page 554-559. IEEE Computer Society, (2005)An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees., , , and . DATE, page 61-68. IEEE Computer Society, (2002)The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks., , and . ICCAD, page 267-274. ACM / IEEE Computer Society, (1998)A low power VLIW processor generation method by means of extracting non-redundant activation conditions., , , and . CODES+ISSS, page 227-232. ACM, (2007)A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions., , , and . Inf. Media Technol., 5 (4): 1110-1121 (2010)Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)., , , and . Inf. Media Technol., 5 (4): 1064-1081 (2010)