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Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.

, , , , , , and . ASP-DAC, page 449-454. IEEE, (2009)

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A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts., , , and . DAC, page 527-532. ACM Press, (1996)Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors., , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2010)A low power VLIW processor generation method by means of extracting non-redundant activation conditions., , , and . CODES+ISSS, page 227-232. ACM, (2007)Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface., , , , , and . ASP-DAC, page 299. IEEE, (2017)Error analysis of an estimation method using RTT for available bandwidth of a bottleneck link., , , and . APNOMS, page 1-3. IEEE, (2013)A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems., , , and . BioCAS, page 1-4. IEEE, (2015)VLSI implementation of a real-time operating system., , , and . ASP-DAC, page 679-680. IEEE, (1997)Effectiveness of the ASIP design system PEAS-III in design of pipelined processors., , , , , and . ASP-DAC, page 649-654. ACM, (2001)VLSI Implementation of Fractal Image Compression Processor for Moving Pictures., , and . EUROMICRO, page 400-409. IEEE Computer Society, (2001)A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions., , , and . Inf. Media Technol., 5 (4): 1110-1121 (2010)