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A Test Method for Finding Boundary Currents of 1T1R Memristor Memories.

, , , , , and . ATS, page 281-286. IEEE Computer Society, (2016)

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Hierarchical Test Integration Methodology for 3-D ICs., , , , , and . IEEE Des. Test, 32 (4): 59-70 (2015)CAD reference flow for 3D via-last integrated circuits., , , , and . ASP-DAC, page 187-192. IEEE, (2010)General Modular Multiplication by Block Multiplication and Table Lookup., and . ISCAS, page 295-298. IEEE, (1994)Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs., , , , , , and . ITC-Asia, page 107-111. IEEE, (2017)DLL-Assisted Clock Synchronization Method for Multi-Die ICs., , , and . ICCD, page 473-476. IEEE Computer Society, (2017)SRAM delay fault modeling and test algorithm development., , , and . ASP-DAC, page 104-109. IEEE Computer Society, (2004)A self-testing and calibration method for embedded successive approximation register ADC., , , , , , , and . ASP-DAC, page 713-718. IEEE, (2011)A built-in self-repair scheme for DRAMs with spare rows, columns, and bits., , , , , and . ITC, page 1-7. IEEE, (2016)On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC., , , , , , , , and . ISVLSI, page 459-464. IEEE Computer Society, (2017)A hybrid ECC and redundancy technique for reducing refresh power of DRAMs., , , , , , , and . VTS, page 1-6. IEEE Computer Society, (2013)