Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor., , , , , , , , and . ISSCC, page 398-399. IEEE, (2007)The IBM Blue Gene/Q interconnection network and message unit., , , , , , , , , and . SC, page 26:1-26:10. ACM, (2011)DSP architecture for cochlear implants., , , , , and . ISCAS, IEEE, (2006)Soft Error Resiliency Characterization on IBM BlueGene/Q Processor., , , , , , , , , and 2 other author(s). ASP-DAC, page 385-387. IEEE, (2014)A 16-bit, low-power microsystem with monolithic MEMS-LC clocking., , , and . ASP-DAC, page 94-95. IEEE, (2006)Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache., , , , , , and . CGO, page 179-190. IEEE Computer Society, (2005)14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC., , , , , , , , , and 36 other author(s). ISSCC, page 254-256. IEEE, (2024)Increasing the number of effective registers in a low-power processor using a windowed register file., , , , , , and . CASES, page 125-136. ACM, (2003)A 16-bit low-power microcontroller with monolithic MEMS-LC clocking., , and . ISCAS (1), page 624-627. IEEE, (2005)Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking., , , , , and . ISCAS, IEEE, (2006)